The present invention relates to software-controlled simulation of a circuit design. More specifically, the present invention provides a method for simulating a circuit design using a block diagram representation of the design in a graphical user interface.
Despite the great variety of software circuit design tools currently available, most circuit designers continue to generate their high level designs using pencil and paper. That is, the designer typically draws by hand in a notebook one or more high level block diagrams which may represent increasingly detailed levels of the circuit design. The current practice is to then take these block diagrams and manually convert them to one or more design files in some design file format, e.g., VHDL or Verilog. The circuit level implementations of the blocks in the block diagrams are then specified in these design files. Tedious manual conversions of this type are typically performed exclusively by one or more full time programmers.
There are computer aided drawing (CAD) tools with which a designer can create high level block diagrams in a graphical user interface. However, such CAD tools do not interface with the design tools used for defining the circuit level implementation of the individual blocks in the diagram. Even with an electronically created block diagram, unrelated design files must be created for the implementation of the individual blocks of the diagram. That is, a block diagram created with a currently available CAD tool is about as useful as a hand drawn block diagram with regard to the circuit level implementation of a design.
Once such design files are fully specified the functional operation of each may be individually simulated by a variety of well known techniques. That is, the operation of a design file written in VHDL may be simulated by the application of VHDL test vectors using a VHDL test bench. If, however, the designer wishes to simulate the operation of some combination of blocks in a high level diagram, an entirely new design file must be constructed which specifies all of the included blocks and their combined external interface. That is, there is currently no way in which the separate design files may be easily combined and simulated. The disadvantages of the current approach are manifest. With the addition of each new simulation design file, the file maintenance function associated with a particular design becomes increasingly complex. That is, the number of design files which must be updated when a change is made to one of the related files increases as the number of combination design files increases. And, as mentioned above with respect to the conversion of hand drawn block diagrams to design files, the creation of these simulation design files is highly labor intensive. Moreover, if related design files are not in the same format, as may be the case where a designer wishes to use a previously generated design file from a design entity library, they cannot be combined into a new design file for simulation until one of the files is completely specified in the same format as the other.
It is therefore desirable to provide a method by which different combinations of blocks in a block diagram may be easily combined and simulated together.